1. Field
The embodiments discussed herein relate to layout of a semiconductor integrated circuit.
2. Description of Related Art
In laying out a design circuit, wiring layer structure information, including wiring width and wiring space for wiring layer, are supplied to an automatic arranging and wiring tool. The automatic arranging and wiring tool outputs layout data for the design circuit.
In verifying the layout, information on the wiring resistance value (R) and the wiring capacitance value (C) for wiring and the layout data of the design circuit are supplied to an RC extraction tool and a result of the RC extraction tool and the layout data are supplied to a delay calculation tool. A result of the delay calculation tool is supplied to a timing analysis tool and the timing analysis tool analyzes the layout data in order to detect violations against constraints on timing.
Related art is disclosed, for example, in Japanese Laid-open Patent Publication No. 2008-28161, Japanese Laid-open Patent Publication No. 2001-265826 and Japanese Laid-open Patent Publication No. 2006-278613.